Deterministic Transistor-Flip Experiments on 1,024 RISC-V Cores

Date: 2026-10-20 (Tuesday, week 43) · Project: AI Foundry / Horace ("Speed to Atoms") · Hub: Horace Hub (tailnet) · Query: Antigravity: deterministic transistor flipping count

Verified on the cards, Wed 21 Oct 2026 (week 43). This page's seven experiments were pre-registered and run on three ET-SoC-1 cards as experiment E61: Verifying the deterministic transistor-flip experiments. - Holds: the sum of an input and an output bit it derived from E46 (50.9 fJ) holds at 50.7 fJ. - Its split does not: a result bit costs 27–30 fJ, not 44, and an operand bit about 20–26 fJ, not 6.5. - Wrong prices: - a carry position costs about 1 fJ, not 14; - fmadd.ps has no zero gate on the vector unit (0.2 pJ, not 8.9); - the Miller patterns show no positive effect; - changing which register is read costs 12–14 times the 32 fJ per bit estimated here. - Right: the vector unit does issue one op per cycle; the measured 0.58–0.61 is the test harness's loop. - The camera does see it: a thermal camera sees the work move between two halves of the die, a +373 mK left/right swap, though not along the shire split this page proposes. - Runs that never happened: its history paragraph and several of its const values describe runs that never took place.

Where a number below disagrees with the verification, the verification has what was measured.

1. Why TensorFMA32 Is an Avalanche — and How 1,024 RISC-V Cores Give Us a Single-Gate Scalpel

The Horace series (Horace Hub, 20 Oct Speed-to-Atoms Plan) sets out to follow a single computation on the Esperanto ET-SoC-1 all the way down to individual transistors, picofarads, and electrons:

In the first bit-flip heat experiments (2026-10-12-bitflip-heat and 2026-10-12-txfma-toggles), we varied the bits of the \(B\) operand inside a 10-instruction TensorFMA32 (fmadd.ps) loop and counted signal transitions in a cycle-accurate Verilator simulation of the 7-stage txfma_top RTL unit. That experiment proved the effect is real and macroscopically visible (27.7 W → 45.7 W, an 18.0 W dynamic span across 1,024 cores at 600 MHz), and anchored the first silicon numbers (15.6–18.6 fJ per counted logic toggle, or 189,000–225,000 electrons at 0.517 V).

Why TensorFMA32 limits how cleanly we can isolate a single transistor flip:

1. 1 Input Bit Flip \(\to\) ~1,050 Internal Toggles (85% in a Wallace Multiplier Avalanche): Flipping a single mantissa bit of \(B\) in fmadd.ps fans out across 12 Booth recoders and cascades through a 24×24 carry-save Wallace multiplier tree, a 75-bit alignment shifter, a 75-bit carry-propagate adder, a leading-zero anticipator (LZA), a normalization barrel shifter, and an IEEE-754 rounder. One input bit flip triggers a chaotic avalanche of ~1,050 internal net toggles.
2. Uncounted Sub-Cycle Combinational Glitches: A Verilator cycle-boundary diff counts whether a wire's final value at cycle \(t\) differs from cycle \(t-1\). Inside a Wallace multiplier tree, partial products arrive across 6–8 unequal gate levels; a node can glitch 0 → 1 → 0 two or three times within a single 1.67 ns clock period without changing its end-of-cycle value.
3. Collinearity Between Clocked Flip-Flops, Multiplier Logic, and Buses: In txfma_top, the four toggle categories (ff_clocked, mult, rest, bus) rise and fall together across FP32 bit masks, leaving a 1.47× spread between the 2-parameter fit (8.8 fF per clocked bit, 11.8 fF per logic toggle) and the 4-parameter fit (8.0 fF per logic toggle), and raising the open question from the 16 Oct post outline: why does a clocked bit appear to cost 8.8 fF, 1.5–3.3× a textbook 7 nm flip-flop (2.7–6.0 fF)?

The Key Architectural Advantage of the ET-SoC-1

Unlike a fixed-function matrix systolic array (such as a TPU MXU or GPU Tensor Core) that can only run fused multiply-accumulate pipelines, the Esperanto ET-SoC-1 is an array of 1,024 general-purpose programmable 64-bit in-order RISC-V cores (Minion) across 32 compute shires (2,048 hardware threads), each equipped with: - A 64-bit scalar integer ALU (add, xor, and, or, sll), and - An 8-lane × 32-bit (256-bit) vector execution unit (VPU) that executes 1-cycle bitwise and integer vector instructions (fnot.pi, fxor.pi, fand.pi, for.pi, fsll.pi, fadd.pi) directly out of the 32-entry × 256-bit Vector Register File (f0..f31) at 600 MHz (6.144 × 10¹¹ vector instructions/second across the chip).

When all 1,024 cores execute a tight unrolled loop of 256-bit vector bitwise instructions (fnot.pi, fxor.pi, fand.pi, for.pi): - Zero carry chain: Bit \(i\) never talks to bit \(i+1\). All 256 bit positions are strictly independent 1-gate-deep slices. - Zero Wallace tree & zero combinational glitches: A 1-stage inverter (fnot.pi) or 2-input NAND/NOR/XOR gate (fand.pi, for.pi, fxor.pi) transitions at most once per clock cycle — sub-cycle multi-path hazard glitches are physically impossible when only one input changes or when an AND gate is masked by 0. - Exact programmable transistor flip count \(k \in \{0, 1, \dots, 256\}\): Alternating two source registers f0 = base and f1 = base ^ mask_k (where popcount(mask_k) = k) flips strictly \(k\) bit-slices per core per clock cycle (\(6.144 \times 10^{11} \times k\) bit flips/second across the chip).

2. Proof Already Hiding in the 3-Card Silicon Dataset (manual.json): The fxor.pi vs. fand.pi / for.pi 32-Bit Output-Toggle Discovery

Before running a single new binary on aifoundry2, we can verify that the 1,024 Minion cores resolve single-gate bit-flip differences using the existing 3-card × 3-pass Instruction Energy Manual dataset (docs/reports/data/2026-09-23-energy-manual/manual.json, Experiment E46, 31 instructions × 3 operand modes: zeros, const, random).

Look at what happens in workloads/enercat/kernel/enercat.c when fxor.pi, fand.pi, and for.pi run in the random operand regime: - All three instructions use the exact same 8-instruction unrolled macro OP8_VV, rotating through the exact same 8 pseudo-random source registers f0..f7 (seeded from 0xdeadbeef, uniform independent bits with \(P(\text{bit}=1) = 0.50\)) and writing to f8..f15: c #define OP8_VV(mnem) \ mnem " f8, f0, f1\n\t" mnem " f9, f1, f2\n\t" \ mnem " f10, f2, f3\n\t" mnem " f11, f3, f4\n\t" \ mnem " f12, f4, f5\n\t" mnem " f13, f5, f6\n\t" \ mnem " f14, f6, f7\n\t" mnem " f15, f7, f0\n\t" - Because consecutive instructions \(i-1\) and \(i\) read from independent random registers (f[i-1], f[i]) and (f[i], f[i+1]): - Input operand vs1 toggles with probability \(2(0.5)(0.5) = 0.50 \implies \mathbf{128.0\text{ bits/op}}\) in all three instructions. - Input operand vs2 toggles with probability \(2(0.5)(0.5) = 0.50 \implies \mathbf{128.0\text{ bits/op}}\) in all three instructions. - On zeros, all three instructions sit at virtually the same clock-tree baseline (13.15 pJ for fxor.pi, 13.16 pJ for for.pi, 13.66 pJ for fand.pi). - Yet on random, fxor.pi burns +7.35 pJ/op above zeros, whereas fand.pi burns +6.00 pJ/op and for.pi burns +5.86 pJ/op (mean +5.93 pJ/op) — a 1.42 pJ/op (24%) gap on the exact same input registers!

Why Does fxor.pi Burn 1.42 pJ More Than fand.pi and for.pi on Identical Random Inputs?

Because Boolean truth tables change the output bit-flip probability on the pipeline result latches and VRF writeback port! - For fxor.pi (\(Y = A \oplus B\)): when \(A, B \sim \text{Bernoulli}(0.5)\), the output has \(P(Y=1) = \mathbf{0.50}\). Between consecutive instructions in OP8_VV, the output bus and pipeline latches flip with probability:

Two-Equation Linear Decomposition from fxor.pi, fand.pi/for.pi, and fnot.pi

Let \(e_{\text{in}}\) be the dynamic energy of flipping one input operand bit (VRF read bitline + source operand bus + logic-gate input capacitance) and \(e_{\text{out}}\) be the dynamic energy of flipping one output result bit (logic-gate output + pipeline result latches + writeback bus + VRF SRAM cell write):

Subtracting the two equations eliminates all 256 input flips and isolates the 32 excess output bit flips:

1. Per Output-Bit Flip (\(e_{\text{out}}\), Gate Output + Pipeline Latch + Writeback Bus + VRF Write):
   \[e_{\text{out}} = \frac{7.35 - 5.93}{128 - 96}\text{ pJ} = \mathbf{44.4\text{ fJ/bit (board)}} = \mathbf{33.7\text{ fJ/bit (die)}} \quad\Longleftrightarrow\quad C_{\text{eff,out}} = \frac{E_{\text{die}}}{\tfrac{1}{2}V^2} = \mathbf{252\text{ fF}} \;\; (\mathbf{407{,}000\text{ electrons}})\]
2. Per Input-Operand Bit Flip (\(e_{\text{in}}\), VRF Read + Source Operand Bus + Gate Input):
   \[e_{\text{in}} = \frac{5.93 - 96(0.0444)}{256}\text{ pJ} = \mathbf{6.52\text{ fJ/bit (board)}} = \mathbf{4.96\text{ fJ/bit (die)}} \quad\Longleftrightarrow\quad C_{\text{eff,in}} = \frac{E_{\text{die}}}{\tfrac{1}{2}V^2} = \mathbf{37.1\text{ fF}} \;\; (\mathbf{59{,}900\text{ electrons}})\]
3. Independent Cross-Check on Unary Inverter fnot.pi (128 input flips + 128 output flips, zero vs2 operand): - Predicting fnot.pi from the (e_in, e_out) pair extracted from fxor.pi and fand.pi/for.pi:
   \[\Delta E_{\text{pred}}(\text{NOT}) = 128\,e_{\text{in}} + 128\,e_{\text{out}} \approx 0.83 + 5.68 = 6.51\text{ pJ (board)}\]
   Wait: why is measured fnot.pi even lower (+5.08 pJ board = 39.7 fJ per input+output bit-slice flip, or 30.2 fJ die = 365,000 electrons)? Because a CMOS inverter (fnot.pi) has 2 transistors per bit (1 PMOS + 1 NMOS, no internal gate node) vs. 10–12 transistors per bit in a 2-input XOR cell (fxor.pi)! The difference between fxor.pi (7.35 pJ), fnot.pi (5.08 pJ), and \(128\,e_{\text{in}} = 0.83\text{ pJ}\) isolates the internal multi-transistor switching inside the 256 XOR cells (~1.44 pJ board / 5.6 fJ per XOR cell)!

3. Interactive Explorer #1: The 7-Rung Structural Complexity Ladder

Click any rung below (Rung 0 to Rung 7) to inspect the active circuit blocks inside each Minion core, compare its 3-card silicon energy measurements (zeros, const, random), and see which physical parameter it isolates.

4. Interactive Explorer #2: Deterministic Transistor-Flip Synthesizer & Live RISC-V Kernel Generator

Use the controls below to dial in a custom deterministic bit-flip experiment across the 1,024 RISC-V Minion cores (E-D1 through E-D7). As you adjust the Input Hamming Flip Count (\(k = 0 \dots 256\)), Output Gate Mask, Domino Carry Length (\(L = 0 \dots 31\)), or Adjacent-Wire Phase Factor (\(k_{\text{adj}} \in [0, 2]\)), the simulator computes the exact transistor/node flip counts per instruction, the predicted card power (W), Minion-rail current (A), electrons per instruction, lock-in thermal signal (mK), and generates the ready-to-compile RISC-V kernel.

4B. Interactive Explorer #3: Bit-Slice Domino, Miller Wire-Coupling & 32-Shire Lock-In Microscope

Switch between the four physical mechanisms below and click Step Clock Cycle (t → t+1) to inspect the exact transistor, carry-chain, inter-wire capacitor (\(C_{\text{adj}}\)), and 32-shire thermal-dipole states on the chip.

5. Seven New Deterministic Transistor-Flip Experiments for aifoundry2

Each experiment below is designed to run inside workloads/enercat (or a dedicated workloads/detflip harness) on aifoundry2 (600 MHz, 32 shires, 0.517 V Minion rail). Every experiment varies one physical transistor/wire mechanism at a time while holding instruction issue rate (1.0 IPC = 614.4 Gops/s), control flow, and memory traffic strictly invariant.

\(k = 0 \dots 256\)">Experiment E-D1: The 256-Bit Bitwise Toggle Synthesizer (fxor.pi & fnot.pi Ping-Pong, \(k = 0 \dots 256\))

• What it isolates: Single-bit-slice switching energy (\(e_{\text{in}} + e_{\text{out}}\)) across \(k \in \{0, 16, 32, 64, 96, 128, 160, 192, 224, 256\}\) bits with zero horizontal carry propagation and zero multi-path combinational glitches.
• How the kernel works:
• In fnot.pi (vd = ~vs1), we load even source registers f0, f2, f4, f6 = 0x00000000 and odd source registers f1, f3, f5, f7 = mask_k, where mask_k has \(k/8\) ones in each of the 8 lanes (0..32 bits per lane).
• Crucial detail — VRF Write vs. Pipeline Latch Toggle Control:
  • In the existing enercat macro OP8_VV, instructions \(0 \dots 7\) write to 8 distinct destination registers f8..f15. If the loop repeats identically every 8 cycles, f8 always receives the same value (~f0), so the pipeline result latches and writeback bus flip every cycle at 600 MHz, while the 256 SRAM bitcells inside f8..f15 never flip after the first iteration!
  • By running two variants of E-D1 — Variant 1A (8-destination f8..f15, constant per-register value) vs. Variant 1B (1-destination f8, f8, f8... or phase-inverted 16-op unroll where f8..f15 invert every iteration) — we subtract Variant 1A from Variant 1B to measure the exact transistor + bitline energy of flipping a 256-bit Vector Register File SRAM entry separately from the pipeline latches and result bus!

Experiment E-D2: The Input-vs-Output Mask Bridge (fand.pi with vs2 = 0 vs. vs2 = 0xFFFFFFFF)

• What it isolates: Separates input operand path + gate-input FET capacitance (\(e_{\text{in}}\)) from gate-output + pipeline result latch + writeback bus capacitance (\(e_{\text{out}}\)) without changing the instruction opcode or input register toggles!
• How the kernel works:
• Alternate vs1 (f0, f1) between 0x00000000 and mask_k (\(k\) bits flipping every cycle at 600 MHz).
• Run A (Output Clamped Low, 0 Output Flips): Set vs2 (f2) to 0x00000000 and execute fand.pi f8, f0, f2 / fand.pi f9, f1, f2.
  • Every cycle, \(k\) bits toggle on the VRF vs1 read port, the vs1 operand bus, and the A-input gates of the 256 NAND2 cells.
  • Because the B-input of every NAND2 cell is held at 0, the NAND2 output stays pinned at 1 and the following inverter output stays pinned at 0 (0 & mask_k = 0)! Zero gate outputs flip, zero pipeline latches flip, zero writeback wires flip!
• Run B (Output Unmasked, \(k\) Output Flips): Change only f2 from 0x00000000 to 0xFFFFFFFF.
  • Now the exact same \(k\) input bits toggle on vs1, AND all \(k\) gate outputs, pipeline latches, and writeback wires toggle every cycle (1 & mask_k = mask_k)!
• Run C (Output Clamped High via for.pi, 0 Output Flips): Execute for.pi with f2 = 0xFFFFFFFF (1 | mask_k = 1). Comparing Run A (fand.pi clamped 0) vs. Run C (for.pi clamped 1) measures the NMOS vs. PMOS input-gate Miller capacitance skew when the gate output is held static!

\(L = 0, 1, 2, 4, 8, 16, 24, 31\)">Experiment E-D3: The Programmable Carry-Chain Domino Wave (fadd.pi, \(L = 0, 1, 2, 4, 8, 16, 24, 31\))

• What it isolates: The exact energy of 1 internal carry-propagation stage + 1 sum bit flip inside the 32-bit integer adder, with input Hamming distance held strictly constant at \(h_{\text{in}} = 1\) bit per lane (8 bits across 256-bit vector)!
• Why fadd.pi is ideal: Unlike fmadd.ps, manual.json proves that fadd.pi has no zero-gating (zeros = 12.68 pJ, const = 12.73 pJ, \(\Delta = +0.05\text{ pJ}\)).
• How the kernel works:
• In each of the 8 lanes (32-bit integer), hold vs1 = A_L = (1u << L) - 1u (a contiguous run of \(L\) ones in bits 0 .. L-1, e.g., 0x0000FFFF for \(L=16\)).
• Alternate vs2 = B between 0x00000000 and 0x00000001 (only bit 0 of vs2 flips each cycle!).
• Watch the deterministic domino wave across each 32-bit lane:
  • When B = 0: \(\text{Sum} = A_L = \mathtt{00\dots0\,\underbrace{11\dots1}_{L\text{ ones}}}\) (carries \(c_1 \dots c_L = 0\)).
  • When B = 1: \(\text{Sum} = A_L + 1 = \mathtt{00\dots01\,\underbrace{00\dots0}_{L\text{ zeros}}}\) (carries \(c_1 \dots c_L = 1\)!).
• Result: Flipping 1 single input bit per lane (\(h_{\text{in}} = 8\) bits total) deterministically flips \(8 \times L\) carry nodes and \(8 \times (L+1)\) sum output bits!
• Plotting card power against \(L \in \{0, 1, 2, 4, 8, 16, 24, 31\}\) gives a straight line whose slope is the exact energy of 1 carry-chain stage + 1 sum bit flip, completely free of input-bus variation (\(h_{\text{in}} \equiv 8\) everywhere)!

\(k_{\text{adj}} = 0, 1, 2\)">Experiment E-D4: Direct Silicon Verification of Stop 6's Miller Wire-Coupling Law (\(k_{\text{adj}} = 0, 1, 2\))

• What it isolates: Stop 6 of the Horace post (16 Oct outline) introduces the physical wire-capacitance equation:
  \[E_{\text{wire}} = \frac{1}{2}\bigl(C_{\text{gnd}} + k_{\text{adj}}\,C_{\text{adj}}\bigr)V^2, \qquad k_{\text{adj}} \in \{0, 1, 2\}\]
  where \(k_{\text{adj}} = 0\) when adjacent wires flip in the same direction (\(\Delta V_{\text{adj}} = 0\)), \(k_{\text{adj}} = 1\) when neighbours are quiet (\(\Delta V_{\text{adj}} = \pm V\)), and \(k_{\text{adj}} = 2\) when adjacent wires flip in opposite directions simultaneously (\(\Delta V_{\text{adj}} = \pm 2V\), the Miller doubling effect). Right now, Stop 6 relies on textbook constants for \(k_{\text{adj}} \in \{0, 1, 2\}\). We can measure \(C_{\text{gnd}}\) and \(C_{\text{adj}}\) directly on the ET-SoC-1!
• How the kernel works:
• Fix the total number of flipping bits at strictly \(k = 128\) bits per 256-bit instruction (fxor.pi or fnot.pi on the VPU bus, and flw.ps on the L1/L2 memory bus) and run three spatial phase patterns:
  1. Pattern \(k_{\text{adj}} \approx 0\) (In-Phase Solid Blocks): Lanes 0..3 flip all 32 bits together in unison (0x00000000 ↔ 0xFFFFFFFF, 128 bits flip), while lanes 4..7 stay at 0. Out of 128 flipping wires, 124 have both left and right neighbours flipping in the exact same direction at the same picosecond (\(k_{\text{adj}} = 0.03 \approx 0\)).
  2. Pattern \(k_{\text{adj}} = 1.0\) (Alternating Quiet-Neighbour Comb): All 8 lanes flip only their even bits (0x00000000 ↔ 0x55555555, \(8 \times 16 = 128\) bits flip), while all odd bits stay fixed at 0. Every single flipping wire is flanked on both sides by a static ground-shield wire (\(k_{\text{adj}} = 1.00\) exact!).
  3. Pattern \(k_{\text{adj}} = 2.0\) (Counter-Phased Miller Checkerboard): Lanes 0..3 alternate between 0x55555555 (0101...) and 0xAAAAAAAA (1010...) while lanes 4..7 stay at 0 (\(4 \times 32 = 128\) bits flip). Every even bit switches \(0 \to 1\) at the exact instant its left and right odd neighbours switch \(1 \to 0\) (\(k_{\text{adj}} = 1.94 \approx 2.0\))!
• What this gives the Horace post: A three-point silicon measurement at constant \(k = 128\) flips (k_adj = 0, 1, 2) that directly separates vertical ground capacitance \(C_{\text{gnd}}\) from lateral wire-to-wire coupling capacitance \(C_{\text{adj}}\) on 7 nm metal!

\(\Delta\text{addr} = 0 \dots 5\)-bits">Experiment E-D5: Register-File Address Decoder & Wordline Driver Isolation (\(\Delta\text{addr} = 0 \dots 5\) bits)

• What it isolates: The 5-bit register address bus, predecoder logic trees, and 256-bit wordline drivers of the Vector Register File (f0..f31) and Scalar Register File (x0..x31).
• How the kernel works:
• Fill all 32 vector registers f0..f31 with 0x00000000 (zeros). Zero data bitlines, zero ALU gates, and zero result buses ever toggle.
• Run fxor.pi with 6 different unrolled register-index sequences where the 5-bit register numbers (vs1, vs2, vd) change by Hamming distance \(\Delta\text{addr} \in \{0, 1, 2, 3, 4, 5\}\) bits per cycle:
  • \(\Delta\text{addr} = 0\): fxor.pi f0, f0, f0 repeated 8× (same wordline stays asserted).
  • \(\Delta\text{addr} = 1\): alternate f0 (00000₂) and f1 (00001₂).
  • \(\Delta\text{addr} = 5\): alternate f0 (00000₂) and f31 (11111₂) — all 5 address bits flip on all 3 ports (15 address bits/op) and two distant wordlines charge/discharge every cycle.

Experiment E-D6: Settling the 8.8 fF Clocked-Bit Mystery (fmadd.ps Zero-Gate vs. fadd.pi)

• What it isolates: Resolves Open Question #1 from the 16 Oct Horace post outline: why does the 2-parameter fit on txfma_top assign 8.8 fF (2.35 fJ) to each clocked bit when fmadd.ps transitions from zeros (12.88 pJ) to const (21.82 pJ, \(\Delta = +8.94\text{ pJ}\))?
• What manual.json already reveals:
• Look at fadd.pi (zeros = 12.68 pJ, const = 12.73 pJ, \(\Delta = +0.05\text{ pJ}\)) and fxor.pi (zeros = 13.15 pJ, const = 13.86 pJ, \(\Delta = +0.71\text{ pJ}\)): in un-gated integer/bitwise units, replacing zeros with a non-zero constant adds almost zero energy because the flip-flops are already clocked on zeros and their D-inputs don't toggle on const!
• By contrast, in fmadd.ps, vpu_ctrl.v contains a clock-gate enable triggered by zero operands: when operands are 0.0f, the clock tree to the 7-stage TensorFMA32 pipeline is gated off (12.88 pJ). When operands become non-zero (const = 21.82 pJ), the clock gate opens and clocks ~3,800 internal pipeline flip-flops plus biases the Booth/Wallace array.
• How E-D6 cleanly separates Clock-Tree Un-Gating from Static-1 Biasing:
• Compare four constant fmadd.ps runs (all with zero cycle-to-cycle data toggles):
  1. 0x00000000 (+0.0f, zero-gate closed),
  2. 0x80000000 (-0.0f, tests whether the sign bit alone opens the zero-gate or whether exp|mant == 0 keeps it closed!),
  3. 0x00800000 (smallest positive normal FP32, \(2^{-126}\): exponent = 1, all 23 mantissa bits = 0 — opens the clock gate while keeping the 24×24 Booth/Wallace mantissa array 96% zero!),
  4. 0x3FFFFFFF (\(1.9999999\): exponent = 127, all 23 mantissa bits = 1 — clock gate open + full static-1 bias in the Booth/Wallace tree).

Experiment E-D7: Spatial Anti-Phase Lock-In Dipole (0.05 Hz) for the P3 Thermal Camera

• What it isolates: Pure transistor-flip heat imaged spatially on the Thermal Master P3 camera (25 Hz, 3.2 mK 5-minute lock-in noise floor) while keeping total chip power (ΔP_card = 0.00 W), instruction issue rate (1.0 IPC), and package/heatsink bulk temperature 100% constant!
• How the kernel works:
• Every hart reads mhartid (identifying whether it sits in West Shires 0–15 or East Shires 16–31) and hpmcounter3 (the 600 MHz cycle counter).
• Every hart executes the exact same infinite fand.pi loop (E-D2) with vs1 alternating 0x00000000 ↔ 0xFFFFFFFF (256 input bits flipping every cycle on every core).
• Every \(10\text{ seconds}\) (\(6 \times 10^9\) cycles, square-wave lock-in frequency \(f_{\text{mod}} = 0.05\text{ Hz}\)):
  • During Half-Cycle A (\(0\text{–}10\text{ s}\)): West Shires set vs2 = 0xFFFFFFFF (256 output bits flip/op \(\to\) high dynamic power), while East Shires set vs2 = 0x00000000 (0 output bits flip/op \(\to\) low dynamic power).
  • During Half-Cycle B (\(10\text{–}20\text{ s}\)): West Shires set vs2 = 0x00000000 and East Shires set vs2 = 0xFFFFFFFF.
• Why this is a breakthrough for thermal imaging:
  • At every instant, exactly 512 cores run E-D2b (high) and 512 cores run E-D2a (low). Total card power never changes (\(\Delta P_{\text{total}} \equiv 0\text{ W}\)), eliminating heatsink thermal drift, fan-curve coupling, and VR efficiency shifts!
  • Meanwhile, ~2.2 W of pure output-transistor switching heat swaps between the West and East halves of the silicon die at 0.05 Hz, creating a phase-locked ~110 mK spatial thermal dipole (>30× above the P3 camera's 3.2 mK lock-in noise floor)!

6. Summary Comparison of the Seven Experiments

7. Ready-to-Run Lab Implementation Plan (aifoundry2)

All seven experiments can be added as operand/kernel modes inside workloads/enercat on aifoundry2 (~/claude, repo et-soc1-prototyping) with zero firmware changes:

1. Extend workloads/enercat/kernel/enercat.c with 12 deterministic sub-tests (op_id = 31..42): - 31..35: E-D1 & E-D2 (fnot.pi, fxor.pi, fand.pi with vs2=0, fand.pi with vs2=0xFFFFFFFF, for.pi with vs2=0xFFFFFFFF) swept across \(k \in \{0, 32, 64, 128, 192, 256\}\). - 36..38: E-D3 (fadd.pi Domino Carry Wave) with \(A_L = (1 \ll L) - 1\) for \(L \in \{0, 1, 2, 4, 8, 16, 24, 31\}\) and \(B\) toggling 0 ↔ 1. - 39..41: E-D4 (fxor.pi Miller Wire Coupling) at fixed \(k = 128\) bits for \(k_{\text{adj}} = 0\) (4-lane solid 0xFFFFFFFF), \(k_{\text{adj}} = 1\) (8-lane 0x55555555 vs 0), and \(k_{\text{adj}} = 2\) (4-lane 0x55555555 ↔ 0xAAAAAAAA). - 42: E-D6 (fmadd.ps Zero-Gate Split) at constant +0.0f, -0.0f, 0x00800000 (\(2^{-126}\)), and 0x3FFFFFFF.
2. Validate in Verilator (txfma_top + Minion VPU RTL in core-et): - Run the Verilator toggle counter on fnot.pi, fxor.pi, fand.pi (vs2=0 vs -1), and fadd.pi (L=0..31) to confirm the 1:1 linear mapping between software bit-mask parameters \((k, L)\) and RTL net toggles.
3. Run E-D7 (0.05 Hz West-East Anti-Phase Dipole) under the Thermal Master P3 Camera: - Record 5 minutes (15 lock-in periods at 20 s period) on aifoundry2 while logging get_card_stats (0.00 W total card ripple) and P3 raw Y16 frames (25 Hz), producing the first lock-in thermal image of pure output-transistor bit flips at constant chip power.